1. Field of the Invention
The present invention relates to integrated circuit (IC) manufacture and more particularly to an apparatus and method of substrate surface treatment for electrolytic or electroless plating of metals or other conductive materials.
2. Description of Related Art
Modern integrated circuits use conductive interconnections to connect the individual devices on a chip or to send and receive signals external to the chip. Common types of interconnections include aluminum (Al) alloy interconnection lines and copper (Cu) interconnection lines coupled to individual devices, including other interconnection lines, by interconnections through vias. In order to enhance interconnect speed and reliability, the semiconductor manufacture industry is moving away from blanket deposition and etch of Al-based metallizations towards single damascene and dual damascene interconnect structures with Cu-based metallizations.
A damascene technique involves forming a via and an overlying trench in a dielectric to an underlying circuit device, such as a transistor or an interconnection line. The via and trench are then lined with a barrier layer of a refractory material. The barrier layer typically serves to inhibit the diffusion of the interconnection material that will subsequently be formed in the via into the dielectric. Next, a suitable seed material is deposited on the wall or walls and base of the via. Suitable seed materials for the deposition of copper interconnection material include copper and nickel. Following seed material deposition, the wafer may be cooled down in an atmosphere containing argon or nitrogen. Next, interconnection material, such as copper, is deposited in a sufficient amount to fill the via and trench using, for example, an electroplating process. Following the deposition of the interconnection material, a chemical-mechanical polishing or etching process is used to remove any interconnection material present outside the trench. If a trench and an underlying via are filled simultaneously with the interconnection metal, the process is known as a dual damascene process.
As IC design extends into submicron range, e.g. 0.18 microns and under, the reliability of copper and copper-based alloy interconnects becomes critical to a proper IC device operation. Conventional Cu-based metallization processes produce wafers that are saturated with pit defects, ultimately leading to less reliable IC devices.